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Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FEATURES
* 2 differential 2.5V/3.3V LVPECL outputs * Selectable CLK0, CLK1 LVCMOS/LVTTL clock inputs * CLK0 and CLK1 can accepts the following input levels: LVCMOS or LVTTL * Maximum output frequency: 267MHz * Part-to-part skew: 250ps (maximum) * 3.3V operating supply voltage (operating range 3.135V to 3.465V) * 2.5V operating supply voltage (operating range 2.375V to 2.625V) * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS85322I is a Dual LVCMOS / LVTTL-toDifferential 2.5V / 3.3V LVPECL translator and a HiPerClockSTM member of the HiPerClocksTMfamily of High Perfor mance Clocks Solutions from ICS. The ICS85322I has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
ICS
BLOCK DIAGRAM
CLK0 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK0 CLK1 VEE
CLK1
ICS85322I
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
85322AMI
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Type Output Output Power Input Input Power Pullup Pullup Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE CLK1 CLK0 VCC
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
4.6V -0.5V to VCC + 0.5 V 50mA 100mA 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 25 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VCC = VIN = 3.465V VCC = VIN = 3.465V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 1.3 5 Units V V A A
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions VCC = VIN = 3.465V VCC = VIN = 3.465V Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time 20% to 80% @ 50MHz 300 267MHz 0.5 Test Conditions Minimum Typical Maximum 267 1.9 250 700 Units MHz ns ps ps
t sk(pp)
tR / tF
odc Output Duty Cycle 40 60 % All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Test Conditions Minimum 2.375 Typical 2.5 Maximum 2.625 25 Units V mA
TABLE 3D. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current
TABLE 3E. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VCC = VIN = 2.625 VCC = VIN = 2.625 -150 Test Conditions Minimum 1.6 -0.3 Typical Maximum VCC + 0.3 0.9 5 Units V V A A
TABLE 3F. LVPECL DC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.65 Typical Maximum VCC - 1.0 VCC - 1.7 0.9 Units V V V
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time 20% to 80% @ 50MHz 300 215MHz 0.7 Test Conditions Minimum Typical Maximum 215 2.1 250 700 Units MHz ns ps ps
tsk(pp)
tR / tF
odc Output Duty Cycle 40 60 % All parameters measured at 133MHz unless noted otherwise. NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65..
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
2V 2V
V CC
Qx
SCOPE
VCC
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
PART 1
Qx nQy
PART 2
CLK0, CLK1 nQ0, nQ1 Q0, Q1
Qy
tsk(o)
tPD
PART-TO-PART SKEW
PROPAGATION DELAY
nQ0, nQ1 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q0, Q1
Pulse Width t
PERIOD
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
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OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B OCTOBER 7, 2003
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ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR APPLICATION INFORMATION
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50 50 1 Zo (VOH + VOL / VCC - 2) - 2 50 VCC - 2V RTT
FOUT
FIN
RTT =
Zo = 50 84 84
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
ground level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85322I. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS85322I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 60.4mW = 147mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.147W * 103.3C/W = 100.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA
FOR
8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT RL 50 VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 1.0V
-V
OH_MAX
) = 1.0V =V - 1.7V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. ))/R ] * (V Pd_H = [(V - (V - 2V))/R ] * (V -V ) = [(2V - (V -V -V )= OH_MAX CC_MAX CC_MAX OH_MAX CC_MAX OH_MAX CC_MAX OH_MAX L L [(2V - 1V)/50] * 1V = 20.0mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85322I is: 269
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Marking 5322AMI 5322AMI Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85322AMI ICS85322AMIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85322AMI
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REV. B OCTOBER 7, 2003
Integrated Circuit Systems, Inc.
ICS85322I
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
REVISION HISTORY SHEET Description of Change Added Termination for LVPECL Outputs section. 3.3V Output Load Test Circuit Diagram, corrected VEE = -1.3V 0.135V to read VEE = -1.3V 0.165V. Updated Output Rise/Fall Time Diagram. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Inputs ratings. Updated 3.3V LVPECL Output Termination Diagrams. Added Termination for 2.5V LVPECL Outputs. Updated format throughout data sheet. Date 5/30/02 8/23/02
Rev A A
Table
Page 8 6 7 2 3 6 7
T2 B
10/7/03
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